Data transmission between circuits on or off chip generally uses either a parallel interface or a serial interface.
A parallel interface has the advantage of permitting a relatively high transmission data rate, but because N lines and a clock line are needed for transmitting N bits of data in parallel, such a solution occupies a relatively large chip area, requires a large number of input/output pins and/or has a relatively high power consumption due to the charging and discharging of the capacitance of each line.
A serial interface has the advantage of using very few data lines, but cannot achieve the same data rates as a parallel interface. Indeed, the maximum transmission rate on a given data line will be limited by the capacitance of the line, the effect of which is to create a low-pass filter. Furthermore, due to the charging and discharging of the line capacitance on each change of state of the transmitted data, serial interfaces tend to consume relatively high energy.
There is thus a need in the art for a transmission interface and method of data transmission not suffering from at least some of the above drawbacks.